Error:Width mismatch in pin_name -- source isError:Width mismatch in pin_name12 -- source is ""zs_dqm_from_the_sdram_0[1..0]" (ID sd_sopc:inst)"

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Error:Width mismatch in pin_name -- source isError:Width mismatch in pin_name12 -- source is ""zs_dqm_from_the_sdram_0[1..0]" (ID sd_sopc:inst)"
Error:Width mismatch in pin_name -- source is
Error:Width mismatch in pin_name12 -- source is ""zs_dqm_from_the_sdram_0[1..0]" (ID sd_sopc:inst)"

Error:Width mismatch in pin_name -- source isError:Width mismatch in pin_name12 -- source is ""zs_dqm_from_the_sdram_0[1..0]" (ID sd_sopc:inst)"
我在用原理图进行NIOSII 硬件部分编程的时候也遇到了这样的问题,现在已经解决了.
官方的解释是：
This is due to a mismatch between the label on a bus and the pin that it is connecting to.For example,if a bus has the label A[8..0] (9-bits wide),and the pin has the label A[7..0] ( 8 bits wide),this error will be generated.This also happens if you use a single dimensional bus label where a multi-dimensional bus label is required,or vice-versa.
大意就是说你的IO口名称（就是原理图中你自己能修改的那个名字）和芯片内的IO口定义的数据宽度不等.经过检查发现NIOSII在原理图设计中使用自动IO生成功能（Generate Pins for symbol ports）时,若模块复杂则会错位,也就是说你的下一个IO口实际上搭到了上一个IO口上,这样不报错才怪.我的解决方法把模块和IO之间的连线全部删掉,然后再手动连起来.重新配置管脚后编译通过

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